The present invention relates to a semiconductor device constructed so that a tunnel current flows between semiconductor layers with a barrier layer held therebetween. It also relates to a low noise amplifier circuit, a mixer, a logic circuit and a memory circuit which use such a semiconductor device as a field effect transistor or a heterobipolar transistor.
Field effect transistors in which a tunnel current flows through the source-drain electrode region are well known as semiconductor devices for causing the tunnel current to flow. Japanese Patent Laid-Open No. 60570/1988, for example, proposes an HEMT (High Electron Mobility Transistor) constructed from GaAs as a channel material. Further, Japanese Patent Laid-Open No. 3467/1986 proposes an InGaAs channel HEMT. Moreover, high power HEMT has been referred to in the Technical Research Report ED91-151 (1991), pp 95.about.99, the Electronic Information Communication Society of Japan. However, no measure to decrease the tunnel current has been taken in any one of the references mentioned above.
As an example of taking steps to decrease the tunnel current, an FET with reduced tunnel resistance between metal in the source-drain electrode region and a semiconductor has been referred to in Japanese Journal of Applied Physics, 25 (1986), pp L865-L867. However, no consideration has been given in that reference to the tunnel resistance between semiconductor layers with a barrier layer held therebetween, unlike the present invention.
As another example of taking into consideration the tunnel resistance between semiconductor layers with a barrier layer held therebetween in the field of art to which the present invention pertains, an HEMT with reduced tunnel resistance between semiconductor layers with a barrier layer held therebetween has been referred to in the Technical Research Report ED90-141 (1990), pp 57.about.63, the Electronic Information Communication Society of Japan. FIG. 2 illustrates this example. As shown in FIG. 2, an undoped InAlAs buffer layer 23, an undoped InGaAs channel layer 24, an undoped InAlAs spacer layer 25, an n-InAlAs carrier supply layer 26 and an undoped InAlAs barrier layer 27 are successively stacked on a semi-insulating InP substrate 22 in the above order. Further, an n-InAlAs resistance reduction layer 28 and an n-InGaAs cap layer 29 are successively piled up on the undoped InAlAs barrier layer 27 in the source drain electrode region. Moreover, a source and a drain electrode are formed on the n-InGaAs cap layer 29, whereas a gate electrode is formed on the undoped InAlAs barrier layer 27. In this case, the n-InAlAs resistance reduction layer 28 held between the n-InGaAs cap layer 29 and the undoped InAlAs barrier layer 27 is used to lower the tunnel resistance.
Source resistance is one of the important performance indexes of an FET. The source resistance is directly related to the gain of the FET and this makes it an important subject to lower the source resistance in order to improve not only RF (Radio frequency) performance but also noise characteristics. In the case of a heterojunction FET, an ohmic contact including tunneling between semiconductor layers via a barrier is employed as in the prior art. A barrier like this is a layer formed to secure gate breakdown voltage, and tunneling via the barrier layer is certainly not neglible in the case of such a heterojunction element partly because successive crystalline growth is ensured and partly because the process of making the element is facilitated. With respect to the tunneling via the barrier, the resistance may be lowered by reducing the barrier height. On the other hand, the barrier has to be kept high enough to secure the source to gate breakdown voltage and to hold the carrier concentration in the channel at a higher level. In other words, it has not been practicably possible to reduce the barrier height beyond a certain point. As a result, importance is attached to decreasing the resistance involved in tunneling as a decisive factor in order to lower the source resistance essential to upgrading the performance of an FET.
With respect to an HBT or a RHET, the emitter and base resistance should be lowered to improve their performance. In order to improve the intrinsic performance of these devices in particular, the base layer has been made more shallow; however, a problem arising from this is that the thinner the base layer is made, the greater the input resistance (base resistance) becomes. Another problem also arises from the fact that the base electrode and the intrinsic HBT area are difficult to join together.
In the case of high power FETs, since the current density in the operating area of a high power FET tends to increase, not only the magnitude of the source resistance but also the ohmic contact poses a problem on a heterojunction FET in particular. For this reason, it has been essential to lower the source resistance and to improve the ohmic contact even in the aforementioned prior art heterojunction FET.
When an FET is applied to a low noise amplifier circuit, for example, the higher the operating frequency becomes, the lower the gain remains. In order to prevent the gain from decreasing, it is common to reduce the negative feedback capacitance (gate-to-drain capacitance) by making the gate width shorter to secure the gain. However, the source resistance increases as the gate width is shortened, thus increasing the noise figure. As a result, satisfactory performance of such a low noise amplifier circuit has not yet been achieved. When, moreover, an FET is used for extra high-speed use, the current gain cutoff frequency and the power gain cutoff frequency should be improved, and this makes it an important subject to lower the source resistance. In addition, the application of similar circuits to HBT and RHET also makes it a critical subject to lower the base resistance.
Nevertheless, the results of attempts at decreasing the tunnel resistance have thus far been insufficient as far as the prior art introduced in the Technical Research Report ED90-141 (1990), pp 57-63, the Electronic Information Communication Society of Japan is concerned.